The design of complex circuits no longer begins with a circuit diagram. Instead, a circuit designer typically will start with a high-level description or representation of the logic functions required for a new circuit. These logic function definitions will often be described using a hardware description language (“HDL”) (e.g., a SystemVerilog, Verilog, VHDL, or other register-transfer level (“RTL”) description) or even using an algorithmic description (e.g., a C++, SystemC, or other algorithmic description). The designer will then use this functional description to generate a lower-level description or representation of the circuit that describes how the desired functionality is to be implemented. This lower-level representation is typically a gate-level netlist, such as a mapped netlist. Furthermore, the mapped netlist may then be placed and routed, thereby generating a placed and routed netlist. If the design is to be implemented by one or more field programmable gate arrays (“FPGAs”), the placed and routed netlist can then be transformed into one or more binary configuration files suitable for programming the FPGAs.
In general, the process of generating a lower-level circuit description or representation (such as a gate-level netlist) from a high-level description of logic function (such as an RTL or algorithmic description) is referred to as “synthesis.” Similarly, a software application used to generate a lower-level circuit description or representation from a high-level description of logic function is referred to as a “synthesis tool.” Furthermore, when the design is to be implemented using one or more FPGAs, the synthesis process is referred to as “FPGA synthesis,” and the synthesis tools for performing the synthesis are referred to as “FPGA synthesis tools.”
An FPGA is a type of integrated circuit device that can be programmed by a user to perform a specific function after it has been manufactured. Because of their flexibility, FPGAs are employed for a wide variety of uses, including telecommunications, digital signal processing, and image and speech recognition. In addition to being employed in end-user products, many designers use FPGAs to emulate a proposed design for an application-specific integrated circuit (“ASIC”). The accuracy of the design can then be tested and verified using the FPGAs before the actual ASIC is manufactured. An FPGA device typically includes an array of configurable logic blocks, routing channels for interconnecting the configurable logic blocks, and programmable switch boxes for connecting the channels. Some FPGA devices also may include other specialized circuit structures, such as memory circuits, input/output logic circuits, and digital signal processor (“DSP”) circuits. With this arrangement, a designer can program the configurable logic blocks and the switch blocks so as to configure the FPGA device to provide the desired functionality.
While a variety of synthesis tools have been available for many years, many of these tools still have some difficulty generating an efficient configuration of circuit components from high-level logic functions. For example, a recent article estimated that some FPGA synthesis tools produce circuit configurations that are 70 to 500 times larger than known synthesis solutions. See Richard Goering, “Huge FPGA Synthesis Gap Seen,” EE Times (Feb. 20, 2006). Inefficient circuit configurations require more area of an FPGA, which in turn may lead to the need for more FPGA devices to implement desired functionality. Further, inefficient circuit configurations may inadvertently create timing problems for the implemented functionality. Similar problems exist for synthesis tools used to implement ASIC designs.
To address these problems, synthesis tool manufacturers continuously seek to develop algorithms that will improve the synthesis process. Due to the complexity and uniqueness of the synthesis algorithms, however, no single synthesis tool is likely to provide an optimal circuit configuration for every given HDL design. Instead, each synthesis tool typically will perform better than other synthesis tools in limited circumstances (e.g., for particular types or portions of circuit designs, or for FPGA synthesis targeting particular types of FPGA architectures).
Accordingly, there is a need for improved synthesis tools that can use multiple synthesis engine configurations (including synthesis engine configurations from different vendors) and can exploit the relative strengths of these various synthesis engine configurations during synthesis.